HM2301D Datasheet, H&M Semiconductor

* RDS(ON)= 0.48Ω @VGS=-4.5V
* RDS(ON)= 0.67Ω @VGS=-2.5V
* RDS(ON)= 0.95Ω @VGS=-1.8V
* RDS(ON)= 2.20Ω @VGS=-1.5V
* Super high density cell design for e.

* Power Management in Note book
* Portable Equipment
* Battery Powered System FEATURES
* RDS(ON)= 0.48Ω.

The +0' is the P-Channel logic enhancement mode power field effect transistors are produced using high cell density, DMOS trench technology. This high density process is especially tailored to minimize on-state resistance. APPLICATIONS
* Powe.